The present invention relates to a semiconductor memory device and, more particularly, to a static type metal-oxide semiconductor memory device which is capable of amplifying a small differential signal of read cycle with high speed and which is suitable for achieving larger scale integration.
FIG. 1 shows the arrangement of a static type metal-oxide-semiconductor memory device in accordance with one embodiment of the present invention. In the figure, the reference numerals 1 and 2 denote memory cell groups (memory planes), respectively. Each of the unit circuits (memory cells) constituting the memory cell groups 1 and 2 consists of four metal-oxide semiconductor transistors (hereinafter referred to as "MOST's ") 4, 5, 6, 7 and resistors 8, 9. The memory cell 3 is accessed by a decoder 12 which drives word lines 10 and 11, and a signal output from the memory cell 3 appears on a pair of data lines 13 and 14 in the form of a small voltage difference. When an ON signal is applied to a terminal Y.sub.1, the small differential signal appears on a pair of common data lines 17 and 18 through a pair of switching MOST's 15 and 16. To the common data lines 17 and 18 are also connected the respective drains of another pair of switching MOST's 15' and 16' which are controlled by an ON signal applied to a terminal Y.sub.2. For this reason, the parasitic capacitance of the common data lines 17 and 18 is undesirably increased, and this prevents the memory device from operating at high speed. In order to solve this problem, it is a general practice to divide the common data lines into a plurality of regions using switching MOST's, thus improving the performance of the memory device. Exemplary FIG. 1 shows a pair of common data lines which is divided into two regions respectively defined by common data lines 17, 18 and 32, 33. The common data lines 32 and 33 are similarly provided with two pairs of switching MOST's 15", 16" and 15"', 16"' which are respectively controlled by ON signals applied to terminals Y'.sub.1 and Y'.sub.2. Accordingly, the above-described small differential signal is selected by turning on either a pair of switching MOST's 19, 20 or 21, 22, and supplied to input terminals 24 and 25 of a sense amplifier 23. MOST's 26, 27, 26', 27' and MOST's 28, 29, 30, 31 are loads which are provided for the purpose of maintaining data lines and common data lines at predetermined potentials, respectively. It should be noted that the reference numeral 34 denotes an output buffer for taking out the output of the sense amplifier 23.
Thus, contrivances such as division of common data lines are considered to improve the performance of the memory device, but it is necessary, in order to further improve the performance, to increase the operating speed of the sense amplifier. The sense amplifier is generally arranged such that a small voltage difference input thereto is converted into a current difference, and this is further converted into a voltage difference again. Accordingly, in order to increase the operating speed, it is necessary to use constituent elements in which current greatly changes in accordance with the input voltage. However, the sense amplifier is formed by employing MOST's which are of the same type as that of MOST's used in the memory planes from the viewpoint of manufacturing process and for the purpose of achieving larger scale integration. Accordingly, the current supply capacity is limited, and this disadvantageously limits the improvement in the operating speed.